DFT Engineer

DFT Engineer

Location: San Jose, CA

Type: Contract

Key responsibilities:

Prove existing design verification methodology, tools and flows 

Development of DFT Test insertion, Verification and Implementation flows.

Maintain Full chip test ( ATE) Plan

 Areas of Test Expertise required:

  • MBIST Testing.
  • @Speed TDF, Path delay & Scan Test
  • Bridging Fault generation
  • Iddq Fault generation
  • AC/DC JTAG Insertion, TAP Controllers and test.
  • Serdes Loop testing
  • Hierarchical DFT
  • ATPG Vector generation and validation.
  • Fluency in test compression and Serializers.
  • Generate the SDC constraints for DFT...
  • Participate in ASIC and FPGA chip bring up on PCB and in systems
  • Involved in RMA debug and 8D.
  • Work with functional teams to generate Functional tests to ensure adequate


5-10+ years of relevant experience

Degree in Electrical or Computer Engineering, graduate level or compensating experience

Fluent in STA & SDC’s

Working knowledge of RTL coding in Verilog

Experience in verifying DDR3/DDR4 interfaces

Scripting experience in PERL, Python, and Shell required, C/C++ preferred.

Experience in development of complex custom ASIC products in advanced process nodes preferably FINFET technologies

Required Experience:

  • DFT: 4+ Years 


Send resume to jobs@eworldsolutions.com with the following information:
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