Physical Design Engineer

Physical Design Engineer

Location: Santa Clara, CA

Type: Full time/Permanent

Looking for a physical design engineer with extensive experience in place and route and timing closure.


  • Work with Physical Design House to take part in Physical synthesis, ECO generation to fix timing/drc violations.
  • Understand and debug timing constraints
  • Create, debug and maintain timing constraints, scripts and methodologies for analysis and runs
  • Purpose and review DFT architectures


5-10 years of experience in place and route, timing closure and DFT architectures with Synopsys or Cadence tools.

Experience in timing closure and place and route is a must.

Experience with Prime Time for Multi-Mode Timing Closure

Experience with process variations (AOCV) and signal integrity for 28nm process node and below

Working knowledge of the place and route flow using ICC/ICC2

RLT synthesis is a plus

Low power design methodology is a plus

Required Experience:

  • Physical Design: 5+ Years 


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