Verification Engineer

Verification Engineer

Verification Engineer


Location: San Jose, CA or El Segundo, CA

Type: Contract

This individual will be a member of the ASIC verification team. Responsibilities will include defining and developing the ASIC verification environment and methodology, developing verification plans from specifications. Candidate will be using advanced verification methodologies, tools and will work in an exciting & dynamic design environment. 

Job Description: 

  • Define verification architecture, develop verification plans, implement verification environment and verify ASIC blocks and subsystems using advanced verification methodologies
  • Meet established content, performance, quality, cost and schedule goals.
  • Define overall verification strategies, methodologies, and simulation environment
  • Work with RTL designers and system architects to develop verification plans based on specifications.
  • Run simulation regressions, analyze and debug failures
  • Generate code coverage and functional coverage reports
  • Create, track, and close Bugs in bug tracking tools
  • Provide verbal and written status reports to manager and/or other staff members

Job Requirements:

  • Bachelors degree in EE or CS is required
  • Experienced, 7 years minimum in ASIC/SoC verification
  • Knowledge and experience in coverage driven verification methodologies.
  • Experienced, 5 year minimum in SystemVerilog and UVM
  • Strong background in Object Oriented Programming
  • Prior experience with UNIX/Linux development environment
  • Experience with simulation environments and debug
  • Scripting languages such as Perl/python
  • Self-motivated energetic team player
  • Ability to excel in fast-paced engineering environment
  • Good communication skills
  • DDR verification is a plus

 Required Experience:

  • Verification: 5+ Years


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