It is crucial to know exactly what feature and the percentage of that feature has been verified at any given time. We take the guess work out of verification by using Metric Driven Verification (MDV). With MDV we annotate the coverage directly on to the feature based verification plan that is viewable by all team members. The process is fully automated and the results quantified, allowing the team to make intelligent decisions on resource distribution and scheduling. We are your verification experts.
Our team of experts has experience in verification planning, testbench architecture, implementation and coverage analysis. We have application experience in many technologies, including storage, networking, video processing and analog mixed signal. Let's get started.
- Coverage Driven Verification
- Assertion Based Verification
- Verification and Test Plans
- Coverage Models
- Coverage Analysis and Closure
- RTL/Gate Simulation
- Analog Mixed Signal Verification
- Methodologies - OVM, UVM, and eRM (TLM Verification)
- Languages - Verilog, VHDL, SystemVerilog, C / C++ SystemC and e
Our team of highly experienced chip designers in microprocessor design, storage and networking applications can help your team with specification, design and implementation. Let's get started.
- SystemC Design and High-level Synthesis
- Micro-Architecture Design
- RTL Design and Synthesis
- IP Integration
- DFT Insertion
- Timing Closure
- Mixed Signal System Design
- System Verilog
- SVA and PSL
- Metric Driven Verification